Signals in typical digital systems have two idealized states; namely, a low voltage state and a high voltage state. Unwanted transitions of a signal from a first voltage state to another, and then back to the first voltage state are often referred to as “glitches.” Ideally, digital systems are designed to be glitch-free. In practice, however, glitches are difficult to eliminate.
Glitches may be caused by many factors including, for example, radiation effects. As such, many circuits are designed to include a level of “radiation hardness,” i.e., an attribute of a circuit indicating the extent to which the circuit withstands nuclear or other radiation. Integrated digital circuits used in space, weapons, or aviation applications are typically designed to be more resistant to radiation than circuits used in other applications, because they are more likely to be exposed to radiation, and because their reliability is often more critical, for example. However, such solid-state circuits may still be vulnerable to radiation effects, such as disturbances caused by single, charged particles present within an ambient environment of the circuit. Some examples of these particles are:                Alpha particles: These are byproducts of the natural decay of elements such as uranium and thorium present in some integrated circuit packaging materials.        Energetic (having kinetic energy) protons, neutrons, electrons, heavy ions, and all the natural elements. These are abundant in intergalactic space, earth orbital space and even at high atmospheric altitudes (e.g., commercial flight altitudes) in a wide range of energies.        
When a charged particle passes through a transistor (or any active electronic device), the particle loses energy by ionizing the medium through which the particle passes, leaving behind a track of hole-electron pairs. The electrons of the pairs will migrate toward high voltage state nodes of the struck transistor, resulting in a discharging current on that node. If the discharging current exceeds the current drive of the transistor holding the high voltage state on that node, the node will transition to an undesired low state. The holes of the pairs will migrate toward low voltage state nodes of the struck transistor resulting in a charging current on that node. If the charging current exceeds the current drive of the transistor holding the low voltage state on that node, the node will transition to an undesired high state. The number of hole-electron pairs created by the particle is finite, so the node voltage disturbance is temporary.
Particle-induced circuit disturbances are random and are commonly referred to as single-event effects (SEEs). The SEEs can take on many forms. If the particle strike results in a bit flip or other form of corruption of stored data, this is known as a single-event upset (SEU), or a soft error. If the particle causes a transient voltage disturbance on a node of a logic circuit, this is known as a single-event transient (SET).
A circuit node will typically return to a desired voltage state after an SET. Thus, an SET, in and of itself, may not be a problem. What is likely to be a problem is the consequence of having a temporary voltage disturbance on a circuit node. As an example, if the node is in a clock network, the SET can generate a false clock pulse in a portion of the system. If the node is in the logic that feeds data to an input of a latch (or other type of a memory element), there may or may not be a consequence from the SET. More particularly, if the data input recovers to the valid state from the SET before the latch closes, there is not likely to be a consequence. However, if the data input does not recover to the valid state from the SET before the latch closes, then the wrong data state is loaded into the latch. As a result, an SET-induced SEU occurs.
The susceptibility of modern integrated circuits to SETs can be heightened by reduced feature sizes of integrated circuits and higher clock speeds. As feature sizes continue to decrease, SETs are more likely to propagate through logic gates as normal logic pulses, causing upsets within logic circuits.
Existing circuits for reducing glitches and SETs have some drawbacks. For example, a stacked MOSFET arrangement can be used to prevent an SET from occurring in some circuits. However, this arrangement does not address suppressing an SET that already exists.
Another example circuit includes a stacked inverter arrangement. However, although a stacked inverter arrangement is hardened against creation of SETs from single particle strikes, the stacked inverter arrangement may similarly fail to detect or suppress SETs generated from upstream combination logic. In particular, a stacked-transistor inverter structure may ensure that there are always at least two “off” transistors between any critical circuit node (i.e., a node that, when disturbed, can cause an upset), and VDD/VSS. Thus, when/if a particle strikes one of the “off” stacked transistors, the other “off” transistor prevents the resulting current from reaching the critical node or from reaching VDD/VSS, and no SET occurs. Although the stacked-gate inverter is hardened against formation of SETs within the inverter itself, the stacked-gate inverter's single-input circuit structure generally does not provide hardening against SETs that may be generated by other logic elements and that may propagate onto the input signal to the stacked-gate inverter. As such, if a SET appears at the input to the stacked-gate inverter, the stacked-gate inverter will typically propagate the SET (or, more particularly, an inverted version of the SET) onto its output as it would any other legitimate logic pulse.
Furthermore, existing designs may require configurations that introduce a severe size penalty on the radiation hardening circuit due to the number of transistors used in the configuration. Thus, it would be desirable to provide a solution that “hardens” logic circuits against SETs that overcomes existing drawbacks.